1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tools for generating integrated circuit (IC) layouts, and in particular to a method implemented by an IC layout CAD tool for synthesizing mixed domain clock trees.
2. Description of Related Art
A typical digital IC includes large numbers of clocked devices (xe2x80x9cclock sinksxe2x80x9d or xe2x80x9csinksxe2x80x9d) such as flip-flops, registers and latches that change state in response to clock signal pulses, and the IC synchronizes state changes in a group of sinks by clocking them with the same clock signal. The IC employs a clock tree, a branching network of conductor and buffers, to fan out a clock signal arriving at one of its input terminals to all of the sinks that are clocked by that clock signal. Given the positions of the sinks within an IC layout, a clock tree synthesis (CTS) tool automatically designs a clock tree for distributing a clock signal to the sinks. A typical CTS tool will initially lay out the conductors forming the clock tree in a way that tries to equalize the distance the clock signal must travel to each sink from an IC input terminal receiving the clock signal from an external source. The CTS tool places buffers (amplifiers) at branch points of the tree sized as necessary to drive all of the buffers or sinks downstream of the branch point. Based on an estimate of the signal path delay in each branch of the clock tree, the CTS tool then xe2x80x9cbalancesxe2x80x9d the clock tree by inserting addition buffers in selected branches of the clock tree to adjust the path delays within those branches to ensure that the clock tree will deliver each clock signal pulse to every sink at nearly the same time. Such balancing of the clock tree helps to minimize the difference (xe2x80x9cskewxe2x80x9d between arrival times of each clock signal pulse at any two sinks.
Inserting a buffer into a clock tree can either increase or decrease signal path delays through the clock tree. Each buffer has an inherent delay which can add to the path delay though the clock tree. But a large buffer producing a large output current can reduce path delay by increasing a rate at which capacitance of clock tree conductors downstream of the buffer is charged. Thus depending on the size and buffer of a buffer inserted within a clock tree, the buffer can either reduce or increase signal path delay through the clock tree. A CTS tool can therefore balance a clock tree by appropriately selecting the number, sizes and positions of buffers it inserts into each branch of the clock tree. Since only a limited range of buffer sizes are available, a CTS tool normally cannot size and place buffers to totally eliminate clock signal skew, but it can keep clock signal skew within some specified acceptable limit.
In a xe2x80x9cmixed domainxe2x80x9d IC, groups of sinks are separately clocked by different clock signals. FIG. 1 depicts a prior art mixed domain IC 10 having N clock signal inputs CLK(1)-CLK(N) at IC pins 12 and providing a separate clock tree 14(1)-14(N) for delivering each clock signal to the set of sinks 16 residing with that clock signal""s domain. In the past, an IC designer specified a maximum allowable skew between arrival times of edges of sinks within each clock domain, and a CTS tool sizes and positions each buffer 18 within each clock tree 14 to limit clock skew within each clock domain to the specified maximum for that domain. A CTS tool could therefore independently design a balanced each clock tree 14 because it is necessary only to satisfy maximum skew constraints for paths to sinks 16 within the same clock domain. Timing skew between paths to sinks 16 residing in different clock domains was not of concern.
In recent years IC designers have begun to assign two or more separate clock signals to the same xe2x80x9cclock groupxe2x80x9d and to try to design clock trees of the same clock group so that a skew between edges of clock signals within the same clock group (i.e. the xe2x80x9cgroup skewxe2x80x99) is limited to a specified maximum. For example a designer might assign clocks CLK(1) and CLK(2) of FIG. 1 to the same clock group, and might want to limit the difference between the path delay of an edge of a clock signal CLK(1) traveling from input pin 12(1) to any given sink 16 within its domain via clock tree 14(1) and the path delay of an edge of a clock signal CLK(2) traveling from input pin 12(2) to any given sink 16 via a clock tree 14(2) to some predetermined maximum allowable group skew. Under such a constraint, a CTS tool that designs clock trees can no longer independently balance them.
As illustrated in FIG. 2, to meet a group skew constraint, a prior art CTS tool synthesizes a balanced clock tree for a first one of the clocks within a group so as to minimize the skew within that clock signal""s domain (step 20). The CTS tool then computes an average path delay between the IC pin receiving that first clock signal and all sinks receiving edges of the first clock signal and establishes that average path delay as a target path delay for a next clock tree of the group to be synthesized (step 22). When the clock group includes another clock signal for which a clock tree has not yet been synthesized (step 24), the CTS tool synthesizes a clock tree for that clock signal and adjusts path delays within its branches so that the total transit time between that clock signal""s input terminal and every sink in its domain matches the target path delay as closely as possible. The average path delay for all sinks in the domains of the two synthesized clock trees is then computed (stem 22) and established as a target path delay for a next clock tree of the group to be synthesized at step 26. The process continues until the CTS tool has synthesized clock trees for all clock signals of the group.
The ability of the prior art approach to keep group skew within acceptable limits is highly dependent on the order in which the CTS tool synthesizes the clock trees. For example if the average path delay for the first clock tree to be synthesized it too short, it may not be possible to synthesize a next clock tree of the group having an average path delay very close to that of the first clock tree to be synthesized. It may be necessary for a CTS tool implementing the method to repeat the synthesis process of FIG. 2 several times, choosing a different order in which to synthesize the clock trees during each repetition or the process, until it discovers an order resulting in an acceptable group skew.
What is needed is a quicker method for synthesizing a balanced group of clock trees having an acceptably limited group skew in a manner in which success does not depend on an order in which the clock trees are synthesized.
The invention relates to a method for synthesizing and balancing two or more separate clock trees assigned to the same clock group so as to keep group clock skew within a predetermined maximum limit. In accordance with the invention, a clock tree synthesis (CTS) tool initially generates a separate, independently balanced, first clock tree design specifying each clock tree. The CTS tool then processes the first clock tree design for each clock tree to estimate an average delay the clock signal it is to convey will experience as the clock signal passes through the clock tree to each sink receiving that clock signal. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures the group clock skew will reside within the predetermined maximum group skew limit.
The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.